Flash memory is commonly used in electronic products. A memory cell in a flash memory array generally contains a control gate, a drain diffusion region, and a source diffusion region on a substrate to form a transistor. The transistor has a floating gate, under the control gate, which forms an electron storage device. A channel region lies under the floating gate, with an insulation layer in the form of a tunnel oxide layer between the channel and floating gate. The energy barrier of the tunnel oxide can be overcome by applying a sufficiently high electric field across the tunnel oxide. This allows electrons to pass through the tunnel oxide, thus changing the number of electrons stored in the floating gate. The number of electrons stored in the floating gate determines the threshold voltage (Vt) of the cell, which represents the stored data of the cell. More electrons stored in the floating gate causes the cell to have a higher Vt. represent the stored data of the cell.
To change the Vt of a cell to a higher or lower value, the number of the electrons stored in the floating gate is increased or decreased by applying proper voltages to nodes which include the control gate, the drain and source regions, and the channel region. This causes electrons to move between one or more of these nodes and through the tunnel oxide layer to the floating gate. Movement of electrons between the channel region and the floating gate is referred to as a “channel operation.” Movement of electrons between the drain or source region and the floating gate is referred as an “edge operation,” since it takes place on an overlap region between the edge of the floating gate and the drain or source region.
Because the MLC enables the storage of multiple data bits per cell, it has become one of the best candidates in mass storage applications that typically require high density such as 512 Mb and beyond. In a typical four-level MLC, the Vt of the cell is divided into four levels to represent data “00”, “01”, “10”, and “11”. Each of the four levels may be programmed serially (i.e., each level is written into the flash memory after the previous level is finished). Therefore, if one cell has four levels, the memory may be programmed three times. Prior to programming, a flash memory array is erased, such that every cell in the array is reset to a default state (e.g., “11”). That is, data may be written into the flash memory in three steps: “00”, “01”, and “10”. “11” is not written because it is the default state after the memory is erased.
FIG. 1 illustrates the serial programming of a four-level memory cell. First, the data to be written may be loaded into a static random access memory (“SRAM”) 101 (e.g., page by page). Each page may comprise a number of multiple-bit words. SRAM 101 may include multiple rows and may include two multiple-bit words 102 and 103 in each row. Once the data is loaded, the two multiple-bit words 102.and 103 may be read from each row.
Once the two multiple-bit words 102 and 103 are read, the program may identify a level to be written (e.g., “01”). First, the corresponding bits of words 102 and 103 may be paired. When the bits are paired, the bits from word 103 (“10 . . . 0110”) represent the Most Significant Bit (MSB), and the bits from word 102 (“10 . . . 1001”) represent the Least Significant BIT (LSB). After pairing the bits, the program may determine which bit-pairs have the value “01.” The program may output an indicator value to an output vector 104, which indicates the bits-pairs that may be programmed. The program may output “0” to output vector 104 for each bit-pair that has the value “01,” indicating that programming is needed. Conversely, the program may output “1” to output vector 104 for each bit-pair that does not have the value “01” (e.g. “00”, “10”, “11), indicating that programming is not needed at this time. Output vector 104 may store the indicator values for each bit-pair. For example, output vector 104 stores “11 . . . 0110”, indicating that the two bits represented by “0” may be programmed.
Once output vector 104 is created, output vector 104 may be driven onto a data bus 105, stored in a latch 106, and used to program a flash memory array 107 according to latch 106. Output vector 104 may also be written into a VSRAM 108 in the beginning of the page program. After output vector 104 is stored in the latch 106, the bit-pairs corresponding to “01” may be written into the corresponding MLCs of flash memory array 107. This step is referred to as a “shot”. SRAM 101 may create the program vector and the first shot program and VSRAM 108 may control subsequent program shots. If the MLC is successfully programmed, the indicator values in VSRAM 108 that were “0” may be changed to “1”, which indicates that the data was successfully written.
Once all page data has been written, the program may verify that the data is correctly written. First, the program may read the page data from a flash memory 107. Then, the program may compare this data with the data that should have been written (e.g., “01” from SRAM 101). This is accomplished by comparing the programmed data with the data that is latched into VSRAM 108. If all bits in VSRAM 108 are “1”, the page data is successfully written, and the program may exit the loop and continue at another level (e.g. “00”, “10”). If any indicators in VSRAM 108 are not “1”, the bits associated with the indicators may be written again into the corresponding MLCs of flash memory array 107. This step of again writing the bit-pairs into the MLCs is referred to as “another shot.” Once those bits are written, the program may compare the read data again with the data that should have been written. This process may continue until all bits have been written and all indicators in VSRAM 108 are “1”.
This process of writing and verifying data results in decreased programming speed. As such, there is a need to increase the programming speed.